1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a multi-channel transistor device and a multi-channel transistor manufactured by the method.
2. Description of the Related Art
As the degree of integration of semiconductor devices, particularly, memory devices, has increased and the design rule has greatly decreased, the available area for forming an active region for a device greatly decreases. As a result, it becomes more difficult to ensure a sufficient length or width for a transistor formed in the active region.
As the channel length of a transistor such as an MOSFET decreases, a short channel effect becomes predominant and adversely affects the characteristics of the transistor. A small active region leads to a small gate length in a transistor, thereby deteriorating the characteristics of the transistor due to punch-through. With reduction in the width of the transistor, current capability Id, which is proportional to the width of the transistor and is inversely proportional to the length, expressed as Id∝W/L, decreases, thereby deteriorating the current characteristics of the device. For these reasons, many suggestions for effectively ensuring a longer effective channel length for a transistor formed in a limited active region have been raised.
One of these suggestions is to form a multi-channel MOSFET, which has a plurality of bar-shaped channels. Multi-channel transistors can have a variety structures but also have limitations to be considered.
In addition, leakage current characteristics, which are affected by a P-N junction formed in the source/drain region of a cell transistor, are problems arising with a reduction in the design rule of semiconductor devices. Leakage current is an important factor as it results in a direct deterioration in transistor characteristics, especially refresh characteristics, of a dynamic random access memory (DRAM). As a solution to the problems arising with leakage current, a device structure with an oxide junction below an active region in a cell area has been suggested.
Along with the suggestion of such a promising device structure, and as methods of manufacturing the same have been suggested, research into a memory cell transistor having a new structure and a method of effectively manufacturing the memory cell transistor is continuing.